Involve in various stages of SOC product development: Participate in RTL, design, verification, synthesis, timing analysis, test pattern generation, backend verification and silicon debug.
Perform aspects of Concept and System Engineering, work with System Architect to define the chip architecture, architecture definition, hardware/software partitioning
Requirements:
BSEE with minimum 5-year or MSEE with minimum 3-year experience in VHDL/Verilog coding (RTL & behavioral), ASSP, ASIC development and verification, DSP and controller architecture
Solid knowledge of ASIC design flow using Verilog/VHDL and EDA tools such as Cadence Verilog_XL/NC-Sim, Synopsys VCS, DC, PT, etc
Candidates with experience in complex SoCs can expect to take over significant responsibility in terms of technical Project Management after a short introduction period
At least 5 years working experience in related field